<![CDATA[FPGADesigner的博客]]>https://blog.csdn.net/FPGADesignerzh-cnhttps://blog.csdn.net/<![CDATA[FPGA基础设计（11）Verilog任务、函数、系统任务、系统函数]]>https://blog.csdn.net/FPGADesigner/article/details/102871583https://blog.csdn.net/FPGADesigner/article/details/102871583FPGADesignerSat, 02 Nov 2019 14:25:35 +0800<![CDATA[FPGA基础设计（10）Verilog行为级建模（过程赋值）]]>https://blog.csdn.net/FPGADesigner/article/details/102784167https://blog.csdn.net/FPGADesigner/article/details/102784167FPGADesignerMon, 28 Oct 2019 16:54:59 +0800<![CDATA[FPGA基础设计（9）Verilog数据类型和表达式]]>https://blog.csdn.net/FPGADesigner/article/details/102630644https://blog.csdn.net/FPGADesigner/article/details/102630644FPGADesignerFri, 18 Oct 2019 19:19:43 +0800<![CDATA[FPGA基础设计（8）Verilog常数赋值、字符串、标识符]]>https://blog.csdn.net/FPGADesigner/article/details/102604599https://blog.csdn.net/FPGADesigner/article/details/102604599FPGADesignerThu, 17 Oct 2019 13:10:05 +0800<![CDATA[MATLAB数字信号处理（3）计算方式生成随机序列]]>https://blog.csdn.net/FPGADesigner/article/details/89479210https://blog.csdn.net/FPGADesigner/article/details/89479210FPGADesignerTue, 23 Apr 2019 19:24:00 +0800<![CDATA[Zynq中lwip“自动协商失败（Auto negotiation error）”的解决办法]]>https://blog.csdn.net/FPGADesigner/article/details/89072317https://blog.csdn.net/FPGADesigner/article/details/89072317FPGADesignerSun, 07 Apr 2019 17:33:19 +0800<![CDATA[学会Zynq（29）SPI协议的理解与初步使用]]>https://blog.csdn.net/FPGADesigner/article/details/88956509https://blog.csdn.net/FPGADesigner/article/details/88956509FPGADesignerMon, 01 Apr 2019 20:27:16 +0800<![CDATA[学会Zynq（28）SPI控制器简介]]>https://blog.csdn.net/FPGADesigner/article/details/88932544https://blog.csdn.net/FPGADesigner/article/details/88932544FPGADesignerSun, 31 Mar 2019 17:57:02 +0800<![CDATA[学会Zynq（23）XADC报警功能与中断使用示例]]>https://blog.csdn.net/FPGADesigner/article/details/88916781https://blog.csdn.net/FPGADesigner/article/details/88916781FPGADesignerSat, 30 Mar 2019 18:32:33 +0800<![CDATA[学会Zynq（27）UART中断驱动模式示例]]>https://blog.csdn.net/FPGADesigner/article/details/88910848https://blog.csdn.net/FPGADesigner/article/details/88910848FPGADesignerSat, 30 Mar 2019 13:04:40 +0800<![CDATA[学会Zynq（26）UART轮询（poll）模式示例]]>https://blog.csdn.net/FPGADesigner/article/details/88877251https://blog.csdn.net/FPGADesigner/article/details/88877251FPGADesignerThu, 28 Mar 2019 20:20:31 +0800<![CDATA[学会Zynq（25）UART的基本使用方法]]>https://blog.csdn.net/FPGADesigner/article/details/88852990https://blog.csdn.net/FPGADesigner/article/details/88852990FPGADesignerWed, 27 Mar 2019 19:16:00 +0800<![CDATA[学会Zynq（24）UART控制器简介]]>https://blog.csdn.net/FPGADesigner/article/details/88805887https://blog.csdn.net/FPGADesigner/article/details/88805887FPGADesignerMon, 25 Mar 2019 20:55:19 +0800<![CDATA[学会Zynq（22）XADC测量片内温度与电源电压]]>https://blog.csdn.net/FPGADesigner/article/details/88796040https://blog.csdn.net/FPGADesigner/article/details/88796040FPGADesignerMon, 25 Mar 2019 15:22:42 +0800<![CDATA[学会Zynq（21）TCP轮询机制（polling）示例]]>https://blog.csdn.net/FPGADesigner/article/details/88778125https://blog.csdn.net/FPGADesigner/article/details/88778125FPGADesignerSun, 24 Mar 2019 16:17:11 +0800<![CDATA[学会Zynq（20）TCP echo服务器（接收回调）]]>https://blog.csdn.net/FPGADesigner/article/details/88777515https://blog.csdn.net/FPGADesigner/article/details/88777515FPGADesignerSun, 24 Mar 2019 15:37:26 +0800<![CDATA[学会Zynq（19）TCP发送Hello World（server模式）]]>https://blog.csdn.net/FPGADesigner/article/details/88776615https://blog.csdn.net/FPGADesigner/article/details/88776615FPGADesignerSun, 24 Mar 2019 14:37:48 +0800<![CDATA[学会Zynq（18）TCP发送Hello World（client模式）]]>https://blog.csdn.net/FPGADesigner/article/details/88775286https://blog.csdn.net/FPGADesigner/article/details/88775286FPGADesignerSun, 24 Mar 2019 12:03:52 +0800<![CDATA[学会Zynq（17）pbuf操作函数介绍与示例程序]]>https://blog.csdn.net/FPGADesigner/article/details/88765028https://blog.csdn.net/FPGADesigner/article/details/88765028FPGADesignerSat, 23 Mar 2019 17:42:56 +0800<![CDATA[学会Zynq（16）UDP echo服务器（接收回调）]]>https://blog.csdn.net/FPGADesigner/article/details/88751502https://blog.csdn.net/FPGADesigner/article/details/88751502FPGADesignerFri, 22 Mar 2019 21:37:59 +0800